Download and update imperix IP for FPGA sandbox

This page provides the imperix IP and other source files required for FPGA development on imperix controllers.

To learn how to use the imperix IP, please refer to the getting started with FPGA page and the imperix IP user guide page.

Download

The following table lists the different imperix IP version available. The minimal Vivado version required is 2022.1.

Upgrade procedure

This section describes how to upgrade the imperix IP from an existing Vivado project.

1. Download the FPGA_Sandbox_template zip file for the targeted SDK version and unzip it.
2. In the <project_dir>/ix_repo/ directory, replaces the interfaces and ips folders with the ones from the freshly downloaded sandbox template.

4. Copy the new constraint file to <project_dir>/constraints/.
   ⚠️If modifications were made to the constraint file (e.g. to use USR pins), these modifications need to be reported to the new constraint file.

5. Open the Vivado project. Remove the old constraint file and add the new one.

6. Upgrade the imperix sandbox IP. It may generate warnings, which is expected.

7. Follow the sections below depending on the used imperix IP version.

Upgrading to 3.9 Rev. 4

When upgrading the imperix IP to version 3.9 Rev. 4 or later, the following changes must be made

1. The interface BBOX was added, make sure to connect it to the top-level interface

2. private_in and private_out size changed, make sure to update the top-level ports accordingly

3. After these changes, re-generate the top-level HDL wrapper. To make sure Vivado apply the change properly, we recommend deleting the top_wrapper.vhd and re-create the HDL wrapper.

Upgrading to 3.9 Rev. 5

The imperix IP version 3.9 Rev. 5 brings the following changes. Additional information are provided after the procedure.

• The SBI and SBO interfaces were replaced by the memory-mapped SBIO_BUS.
  The provided VHDL module sbio_registers.vhd makes the bridge between the SBIO_BUS and the traditional SBI and SBO interfaces that were present in the imperix IP 3.9 Rev. 4 and earlier
• The sbio_interconnect .vhd was added for convenience

Upgrade procedure

1. In <project_dir>/ix_repo/
   – replace AXIS_interface.vhd
   – add sbio_interconnect.vhd and sbio_registers.vhd

2. If using the AXI-Stream interface (AXIS_interface.vhd)
   
   In Vivado, click Refresh Changed Modules then reconnect the SBIO_BUS interface.

3. If using SBI and SBO registers
   The provided VHDL module sbio_registers.vhd makes the bridge between the SBIO_BUS and the traditional SBI and SBO interfaces that were present in the imperix IP 3.9 Rev. 4 and earlier.

What’s new in 3.9 Rev. 5 (SDK 2024.2)

The SBI and SBO interfaces were replaced by the memory-mapped SBIO_BUS.
In the future, this bus allows addressing up to 1024 registers as well as using interconnects for an increase in flexibility.

The provided VHDL module sbio_registers.vhd makes the bridge between the SBIO_BUS and the traditional SBI and SBO interfaces

The sbio_interconnect was added for convenience

The SBIO interconnect increases the number of SBIO_BUS interfaces, allowing to connect multiple SBIO modules as illustrated below.

The address mapping of the SBIO interconnect is shown below, it divides the SBIO addressable range in 4 smaller areas.

As an example, to write to SBO_reg_03 of an sbio_registers block connected to S2_SBIO_BUS, The user has to use an SBO block to register number 512+3=515.

What’s new in 3.10 (SDK 2024.3)

In version 3.10, the IP becomes configurable:

• The SFP port can be repurposed by the user, to use the Aurora protocol for instance.
• Unused resources can be removed, to save up FPGA resources.

Repurposing the SFP ports

Checking the box “Disable RealSync on SFP” will remove the imperix RealSync logic for the selected SFP and free the GTX transceiver. The SFP can then be repurposed by the user to implement its own communication, using the Aurora 8B10B IP for instance.

Checking the box “Disable RealSync on SFP 0” will reveal the txn, txp, rxn, and rxp ports, as well as the GT interface, which contains the Shared Logic ports.

The image below shows how an Aurora 8B10B IP can be used on the SFP port. Make sure that the “GT Refclk” parameter is set to 250 MHz and that the “include Shared Logic in example design” is checked. The other parameters can be changed freely.

An example of block design showing how to set up communication with Aurora is available here.

Saving FPGA resources

Some modules can be removed from the design to free FPGA resources. For now, only PWM modulators can be removed, but in the future we intend to allow disabling additional modules (for instance modules only used by the TPI8032) to make even more FPGA resources available to the user.

The table below summarize the resources saved for each option. The percentages indicate the percentage of resources used by the component compared to the total resources available in the FPGA. Checking all the boxes frees around 18% of FPGA resources. With all the boxes ticked, the imperix IP takes around 30% of the FPGA resources available in the FPGA.