Download and update imperix IP for FPGA sandbox
Table of Contents
This page provides the imperix IP and other source files required for FPGA development on imperix controllers.
To learn how to use the imperix IP, please refer to the getting started with FPGA page and the imperix IP user guide page.
Download
The following table lists the different imperix IP version available.
C++ or ACG SDK | imperix IP version | Minimal Vivado version required | Download |
3.4.x.x 3.5.x.x | 3.4 Rev. 1 | 2019.2 | sandbox_sources_3.4_3.5.zip |
3.6.x.x | 3.6 Rev. 1 | 2019.2 | sandbox_sources_3.6.zip |
3.7.x.x | 3.7 Rev. 1 | 2021.1 | sandbox_sources_3.7.zip |
3.8.x.x | 3.8 Rev. 1 | 2022.1 | sandbox_sources_3.8.zip |
internal only | 3.9 Rev. 1 to 3 | 2022.1 | internal only |
2024.1 | 3.9 Rev. 4 | 2022.1 | FPGA_Sandbox_template_3.9rev4.zip ā ļøRead upgrade section below |
2024.2 | 3.9 Rev. 5 | 2022.1 | FPGA_Sandbox_template_3.9rev5.zip ā ļøRead upgrade section below |
Upgrade procedure
This section describes how to upgrade the imperix IP from an existing Vivado project.
- Download the FPGA_Sandbox_template zip file for the targeted SDK version and unzip it.
- In the <project_dir>/ix_repo/ directory, replaces the interfaces and ips folders with the ones from the freshly downloaded sandbox template.
- Copy the new constraint file to <project_dir>/constraints/.
ā ļøIf modifications were made to the constraint file (e.g. to use USR pins), these modifications need to be reported to the new constraint file.
- Open the Vivado project. Remove the old constraint file and add the new one.
- Upgrade the imperix sandbox IP. It may generate warnings, which is expected.
- Follow the sections below depending on the imperix IP version.
Upgrading to 3.9 Rev. 4
When upgrading the imperix IP to version 3.9 Rev. 4 or later, the following changes must be made
- The interface
BBOX
was added, make sure to connect it to the top-level interface
private_in
andprivate_out
size changed, make sure to update the top-level ports accordingly
- After these changes, re-generate the top-level HDL wrapper. To make sure Vivado apply the change properly, we recommend deleting the
top_wrapper.vhd
and re-create the HDL wrapper.
Upgrading to 3.9 Rev. 5
The imperix IP version 3.9 Rev. 5 brings the following changes. Additional information are provided after the procedure.
- The SBI and SBO interfaces were replaced by the memory-mapped SBIO_BUS.
The provided VHDL module sbio_registers.vhd makes the bridge between the SBIO_BUS and the traditional SBI and SBO interfaces that were present in the imperix IP 3.9 Rev. 4 and earlier - The sbio_interconnect .vhd was added for convenience
Upgrade procedure
- In <project_dir>/ix_repo/
– replace AXIS_interface.vhd
– add sbio_interconnect.vhd and sbio_registers.vhd
- If using the AXI-Stream interface (AXIS_interface.vhd)
In Vivado, click Refresh Changed Modules then reconnect the SBIO_BUS interface.
- If using SBI and SBO registers
The provided VHDL modulesbio_registers
.vhd
makes the bridge between theSBIO_BUS
and the traditionalSBI
andSBO
interfaces that were present in the imperix IP 3.9 Rev. 4 and earlier.
Changes brought by version 3.9 Rev. 5
The SBI
and SBO
interfaces were replaced by the memory-mapped SBIO_BUS
.
In the future, this bus allows addressing up to 1024 registers as well as using interconnects for an increase in flexibility.
The provided VHDL module sbio_registers
.vhd
makes the bridge between the SBIO_BUS
and the traditional SBI
and SBO
interfaces
The sbio_interconnect
was added for convenience
The SBIO interconnect increases the number of SBIO_BUS interfaces, allowing to connect multiple SBIO modules as illustrated below.
The address mapping of the SBIO interconnect is shown below, it divides the SBIO addressable range in 4 smaller areas.
As an example, to write to SBO_reg_03 of an sbio_registers
block connected to S2_SBIO_BUS, The user has to use an SBO block to register number 512+3=515.