Table of Contents
This page provides the imperix sources files required to start programming the FPGA on imperix controllers. The provided archive contains the imperix firmware IP and sandbox template creation script, as well as helper modules.
The template creation procedure is detailed in the getting started with FPGA page.
Downloads
Starting with SDK 2024.3, upgrading the SDK no longer requires regenerating the FPGA bitstream.
Regenerating the bitstream is only required in the following scenarios:
– To access new features and improvements (see the change logs below)
– When using imperix IP (IXIP) Rev 3.9 and older (SDK 2024.2 and older)
For detailed instructions, PN174 provides a step-by-step guide on upgrading an FPGA design.
Regenerating the bitstream is only required in the following scenarios:
– To access new features and improvements (see the change logs below)
– When using imperix IP (IXIP) Rev 3.9 and older (SDK 2024.2 and older)
For detailed instructions, PN174 provides a step-by-step guide on upgrading an FPGA design.
| Compatible SDK versions | Generation 4 B-Box 4 | Generation 3 B-Box RCP3.0, B-Box Micro, B-Board PRO, TPI8032 |
| 2026.1 | IXIP 4.0 Rev. 0 FPGA_Sandbox_template_4.0rev0.zip | IXIP 3.10 Rev. 3 FPGA_Sandbox_template_3.10rev3.zip |
| 2026.1 2025.2 2025.1 | Not applicable. | IXIP 3.10 Rev. 1 FPGA_Sandbox_template_3.10rev1.zip |
| 2026.1 2025.2 2025.1 2024.3 | Not applicable. | IXIP 3.10 Rev. 0 FPGA_Sandbox_template_3.10rev0.zip |
Imperix recommends using the most up to date SDK and sandbox source files. The latest SDK installer is available on the download software installers page.
Change logs
New in 3.10 Rev. 0
- Repurposing the SFP ports
One or multiple SPF ports can now be detached from RealSync and the corresponding GTX transceivers accessed via additional ports on the imperix firmware IP. The SFP ports can therefore be used for custom communication, using Aurora 8B10B for instance. - Saving of FPGA resource
Unused modulators can bow be disabled in the imperix firmware IP, significantly reducing the resource consumption of the IP in the FPGA. Users with large custom FPGA designs might take advantage of it to extend their design even further.
New in 3.10 Rev. 1
- Improved configurability of the RES block
The resolution and excitation frequency of the resolver can now be changed. The default values are 12-bit and 10 kHz, as set in the previous firmware versions.
New in 3.10 Rev. 2
Internal version.
New in 3.10 Rev. 3
- Support for remote debugging over the network
Thanks to the support of Xilinx Virtual Cable (XVC), it is now possible to instantiate and connect to on-chip Integrated Logic Analyzer (ILA) cores via Ethernet. This provides access to the internal FPGA signals without any physical JTAG cable, greatly facilitating the debug of FPGA logic. Find more information in How to debug an FPGA design. - Propagation of Ethernet between devices at full gigabit speed
An upgrade of the Ethernet-over-RealSync protocol – from Mbps to Gbps – allows inter-device traffic to reach the Gigabit speed in master-slave and multi-master setups.
Archives content
The content of the archives follows the following structure.
| /constraints/ | Constraints associated to the imperix firmware, mainly the assignation of top-level ports to physical package pins. |
| /hdl/ | Ready-to-use VHDL helper modules, detailed in the next section, provided by imperix for convenience. |
| /ix_repo/ | Imperix firmware IP, called the IX IP, that encaspulates the imperix firmware and provides access to several internal interfaces – such as the analog measurements – to interact with the firmware from the sandbox ; also contains interface definition files for Vivado. |
| /scripts/ | Generation scripts to automatically create, open and configure a ready-to-use Vivado project template, simplifying the initial setup. |
| /vivado/ | Location of the projects created via the generation scripts from /scripts/. |
VHDL helper modules
AXIS_interface.vhd | Provides AXI4-Stream interfaces for ADC measurement and data exchange with the CPU. The module is further documented in PN126 (retrieving ADC measurements) and in PN128 (exchanging data between CPU and FPGA). |
AXIS_64_interface.vhd | Extended version of the AXIS_interface.vhd. Provides 64x AXI4-Stream interfaces to exchange data with the CPU. |
AXIS_to_reg.vhd | Exposes the data of an AXI4-Stream interface as a register, updating its value whenever the input data is valid. |
resets.vhd | Generates reset pulses based on the firmware synchronization pulse and CPU state. |
sbio_registers.vhd | Gives access to 64x 16-bit registers that can be read/written from the user code running in the CPU using SBI and SBO blocks. The module is further documented in PN128 (exchanging data between CPU and FPGA). |
sbio_256_registers.vhd | Extended version of the |
sbio_interconnect.vhd | Splits the 1024-addresses range of the CPU-FPGA communication into four smaller 256-addresses ranges. Allows to connect multiple SBIO modules simultaneously. |
user_cb_pwm.vhd | Carrier-based PWM modulator written in VHDL. The module is further documented in PN127. |
Legacy IPs for older SDKs
| C++ or ACG SDK | imperix IP version | Minimal Vivado version required | Download |
| 2024.2 | 3.9 Rev. 5 | 2022.1 | FPGA_Sandbox_template_3.9rev5.zip |
| 2024.1 | 3.9 Rev. 4 | 2022.1 | FPGA_Sandbox_template_3.9rev4.zip |
| internal only | 3.9 Rev. 1 to 3 | 2022.1 | internal only |
| 3.8.x.x | 3.8 Rev. 1 | 2022.1 | sandbox_sources_3.8.zip |
| 3.7.x.x | 3.7 Rev. 1 | 2021.1 | sandbox_sources_3.7.zip |
| 3.6.x.x | 3.6 Rev. 1 | 2019.2 | sandbox_sources_3.6.zip |
| 3.5.x.x 3.4.x.x | 3.4 Rev. 1 | 2019.2 | sandbox_sources_3.4.zip |
By Benoît Steinmann • August 13, 2021 • PN168
